Secure integrated circuits (ICs) have to provide a fall-back scenario for unsuccessful or broken communication. Data which is rendered invalid must not be transferred into the memory space where it will actually be used by a program.
This feature is most commonly implemented by providing a dedicated transaction buffer. Such buffers are under exceptional read/write access with respect to other EEPROM cells in the system, which makes them vulnerable to failure from exceeding the maximum read/write cycle count of the EEPROM cells. Especially index counter, single bytes or words, are under exceptional stress.
The lifetime of secure integrated circuits is measured in guaranteed read/write cycles to EEPROM memory cells. Due to the nature of the applications running on these integrated circuits, for example, requiring to transmit data securely, some cells are under exceptional stress. The lifetime of the device is then defined by the worst cell in the integrated circuit.
Prior art document DE 35 17 087 A1 discloses an EEPROM divided into at least twice as many memory sectors as required. Two sectors are combined into one memory location. The use of one of the sectors in a memory location is counted and when a threshold is reached, the other sector is selected for use.
Prior art document EP 0 544 252 A2 discloses a memory divided into a number of memory areas. When a request to update data in a memory area is generated, the memory area with the data is compared in erasing cycles to an empty memory area. If the empty memory area has a lower count of erasing cycles the data is written to the empty memory area and the address is changed to this memory area.
Prior art document WO 99/33057 A1 discloses dividing a non-volatile memory into sectors. A sector is composed of subsections. When a write is requested to a sector the appropriate subsection is selected and a counter is incremented counting erasing cycles. When the counter reaches a threshold, the next subsection is used.
Prior art document U.S. Pat. No. 7,363,421 B2 discloses a method for wear leveling of a flash memory. Each block has an erase count and when new data are written, the block with the lowest count is selected.
The above-described processes according to the prior art do not relate to memory cells but relate to memory blocks or to memory devices and are based on counts which have to be stored in a non-volatile way; in this context, a counter for each single memory cell would not be reasonable.
However, with the counts being stored in the controlled sector, namely in the single memory cell which is anyway under exceptional stress, i.e. where most erase/write operations take place, it is not unlikely that this counter memory cell is already of bad or low quality even if other areas of the controlled sector are still of good or excellent quality.